Design Verification Lead

Role Overview This is a leadership role for a highly experienced Design Verification engineer who can drive end-to-end verification for a block, subsystem, or SoC. The ideal candidate combines deep hands-on expertise in SystemVerilog/UVM with strong technical leadership, a track record of mentoring teams, and the ability to deliver robust verification outcomes on complex semiconductor programs. Core Responsibilities Own and lead verification for a block, subsystem, or SoC from planning through …